Page  124 ï~~SERIES PHI REAL TIME DIGI' Lawrence Casserley Lawrence Electronic Chiltern Cottage, Ha Bledlow Ridge, Bucks ABSTRACT: The Series Phi Signal Processor utiliE processing architecture s rate structure of CSound provides an efficient, ye for real time digital S audio. files The Phi Compili e: based on the Csou into the correct code in processors. In order t( I I - - -. a - _ - -

Page  125 ï~~This multi-processor architectu reasons. Experience with earlie on the TMS32010 showed that a c the cost of such a card lies I interfacing. The TMS320C26 has run most of its program wit] Therefore very little additiona a card with two processors. It the k-rate level requires more first be apparent and that tl maximum efficiency. It was deen rate power remain proportional system grows, so the host proce it would quickly be overburd equally important that the a-r; be burdened with these tasks, hi three tier architecture w nrnneccnr.

Page  126 ï~~FIG1 - PHI DSP SYSTE ST ATARI ST (or other mi HU RATE PROCESSI